(1) Field of the Invention
The present invention relates to the field of electronic design automation (EDA) for integrated circuits. More specifically, the present invention relates to the field of computer controlled systems and software for system and hardware simulation and circuit synthesis.
(2) Prior Art
Advances in processing technology have allowed a high-level of integration within modern integrated circuits and the advances have brought new challenges in the design of digital integrated circuit systems. For instance, higher integration has spurred a trend to integrate entire complex systems consisting of heterogeneous mixtures of hardware and software components into "system-on-a-chip" designs. This trend challenges computer aided design (CAD) tool developers to provide CAD tools that can support the designs required for these hardware/software heterogeneous systems. Specifically, as digital circuits and systems become more complex, system designers are becoming increasingly concerned about the system modeling tools they use and the degree to which these tools have an impact on overall productivity and the quality of hardware designs they produce. In addition, designers today want to be able to quickly produce a working model of the intended hardware, simulate it with the rest of the system and, if needed, synthesize and/or formally verify the design for specific properties (e.g., to test whether or not the design meets timing, area, power constraints, etc.).
Several researchers have proposed various methodologies for the hardware/software co-design of digital systems. Commercial tools have addressed some of the issues in co-design such as hardware/software co-simulation. However, these systems and methodologies require specialized software with specialized libraries and thereby increase the number of tools a circuit designer is required to learn to design integrated circuits. Moreover, none of these systems and methodologies have provided the use of a high-level programming language for performing both system and circuit design and simulation.
To this end, one of the most pressing issues in hardware/software co-design is that of design entry, e.g., the lack of a single language in which to describe both hardware and software components. A single language would facilitate seamless hardware/software co-simulation and help in circuit synthesis. Moreover, a single language would facilitate the step-by-step refinement of a system design down to its components. As such, it would be advantageous to provide a single language framework in which the designer can describe both hardware/software components of the circuit design. The present invention provides for such advantageous functionality.
Growth in the use of programming languages for system-level models is increasing because of the familiarity and experience of system designers with general-purpose high-level programming languages. Today, a system designer writes only the system-level models of an integrated circuit (IC) device in a high-level programming language and then performs an inefficient and often error-prone translation of that IC design into another language for circuit synthesis. For instance, the designer can estimate system performance and verify functional correctness of the IC designs using commonly available software compilers of the high-level programming language. However, to implement the IC design using circuit synthesis, the designer then needs to manually translate those parts of the model that will become hardware into a synthesizable subset of a specialized hardware description language (HDL), such as Verilog or VHDL. The HDLs are geared specifically toward hardware modeling and most common semantic extensions govern the use of structural components, exact event timing and concurrency of operations. These elements are largely absent in most high-level software programming languages. The translation from a high-level software programming language into a specialized HDL is often tedious and error-prone. Therefore, it would be advantageous to provide a single language framework that delegates the complexities of handling hardware semantics to a library of class and methods, thereby facilitating the development of hardware descriptions from existing code of a high-level programming language. The present invention provides such advantages.
Another reason for needing a translation between a high-level software programming language into a specialized HDL to perform hardware modeling is that HDLs have largely not been applied for system modeling. The use of HDLs in system modeling, architectural evaluation and hardware/software co-design has been mixed at best. One reason for this disadvantageous result has been the overhead of event processing required within an HDL. Another reason is that HDLs often do not have the facilities to describe software in an efficient and natural way. Further, HDLs typically have poor facilities to describe data structures. Also, they do not integrate seamlessly to existing software libraries. HDLs are often interpreted and therefore slow and their event and signal semantics make it difficult to compile HDLs to code that is an efficient to those generated by optimizing software compilers. Therefore, it would be advantageous to provide a single language framework for system and hardware modeling that is not HDL based. The present invention provides such advantages.
Accordingly, the present invention provides a single programming framework or application program interface (API) that is based on a high-level programming language to perform both system and hardware modeling (including architectural evaluation and hardware/software co-design). The present invention provides the above using the C++ high-level programming language and a specialized set of library classes and methods that create a specialized application program interface for EDA applications. These and other advantages of the present invention not specifically described above will become clear within discussions of the present invention herein.